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Maintenance only
Features Description
Addressing The UD61256 is a dynamic WriteRead-memory with random access. FPM facilitates faster data operation with predefined row address. Via 9 address inputs the 18 address bits are transmitted into the internal address memories in a time-multiplex operation. The falling RASedge takes over the row address. During RAS Low, the column address together with the CAS signal are taken over. The selection of one or more memory circuits can be made by activation of the RAS input. Read-Write-Control The choice between Read or Write cycle is made at the W input. HIGH at the W input causes a Read cycle, meanwhile LOW leads to a Write cycle. Both CAS-controlled and W-controlled Write cycles are possible with activated RAS signal.
UD61256
256K x 1 DRAM
Data Output Control The usual state of the data output is the High-Z state. Whenever CAS is inactive (HIGH), Q will float (High-Z). Thus, CAS functions as data output control. After access time, in case of a Read cycle, the output is activated, and it contains the logic 0" or 1". Q is then valid until CAS returns into to inactive state (HIGH). The memory cycle being a Read, Read-Write or a Write cycle (W-controlled), Q changes from High-Z state to the active state (0" or 1"). After the access time the contents of the selected cell is available, except for the Write cycle. The output remains active until CAS becomes inactive, irrespective of RAS becoming inactive or not. The memory cycle being a Write cycle (CAS-controlled), the data output keeps its High-Z state throughout the whole cycle. This configuration makes Q fully controllable by the user merely through the timing of W. The output storaging the data, they remain valid from the end of access time until the start of another cycle.
F Dynamic random access memory F F F F F F F F F F
262144 x 1 bit manufactured using a CMOS technology RAS access times 70 ns, 80 ns TTL-compatible Three-state output 256 refresh cycles 4 ms refresh cycle time FAST PAGE MODE Operating modes: Read, Write, Read - Write, RAS only Refresh, Hidden Refresh with address transfer Power Supply Voltage 5 V Packages PDIP16 (300 mil) SOJ20/26 (300 mil) Operating temperature range 0 to 70 C Quality assessment according to CECC 90000, CECC 90100 and CECC 90112
Pin Configuration
Pin Description
A8 D W RAS n.c.
1 2 3 4 5
26 25 24 23 22
V CAS Q
Signal Name
A8 D W 1 2 3 4 5 6 7 8 16 15 14 VSS CAS Q A6 A3 A4 A5 A7 A0 - A8 D W RAS UCC USS CAS Q n.c.
Signal Description
Address Inputs Data Input Read, Write Control Row Address Strobe Power Supply Voltage Ground Column Address Strobe Data Output no connected
A6 n.c.
RAS A0 A2
PDIP
13 12 11 10 9
SOJ
A1 VCC 18 17 16 15 14 n.c. A3 A4 A5 A7
n.c. A0 A2 A1 VCC
9 10 11 12 13
Top View
Top View December 12, 1997 1
UD61256
Block Diagram
CAS Output Control Decoder 1 out of 4 Data Output Amplifier 4 Write-Read Amplifier Data W Write-Read Control Q
D
Data Input Amplifier
RAS
Clock Generator 128 Kbit Array with Sensor Amplifier 128 Kbit Array with Sensor Amplifier Row Decoder VCC VSS Column Decoder
A0 A1 A2 Address Input A3 A4 A5 A6 A7 A8 M U X A8X A8Y
Row Decoder A0X to A7X A0Y to A7Y
Operation Address Function Stand-by Read Write Read-Write 1st cycle 2nd cycle 1st cycle 2nd cycle 1st cycle 2nd cycle RAS H L L L L L L L L L L Read L H L Write L H L
*) Transfer of Refresh Address required
Data C X D X X Input Data Input Data X X Input Data Input Data Input Data Input Data X Q High-Z Output Data High-Z Output Data Output Data Output Data High-Z High-Z Output Data Output Data High-Z Output Data High-Z
CAS X L L L HL HL HL HL HL HL H L L
W R X H L HL H H L L HL HL X H L 2 Row Row Row Column Column Row Row X Row Row Row Row
Column Column Column Column Column Column Column Column Column
FPM Read
FPM Write
FPM Read-Write RAS only Refresh HIDDEN Refresh*)
X Input Data
December 12, 1997
UD61256
Characteristics All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and operating temperature range indicated below.
Absolute Maximum Ratings Power Supply Voltage Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature
Remarks: see page 7
1) 1)
Symbol VCC VI VO IO PD Ta Tstg
Min. -0.5 -1.0 -1.0 -50
Max. 7.0 7.0 7.0 50 1
Unit V V V mA W C C
0 -55
70 125
Recommended Operating Conditions Power Supply Voltage Input Low Voltage Input High Voltage
Remark: see page 7
1)
Symbol VCC VIL VIH
Min. 4.5 -1.0 2.4
Max. 5.5 0.8 5.5
Unit V V V
Capacitances Input Capacitance A0 to A8, D Input Capacitance RAS, CAS, W Output Capacitance
Conditions
Symbol CI1 CI2 CO
Min.
Max. 6 7 7
Unit pF pF pF
VCC VI f Ta
= 5.0 V = VSS = 1 MHz = 25 C
All pins not under test must be connected with ground by capacitors.
December 12, 1997
3
UD61256
Static Characteristics Min. Conditions Symbol 07 Power Supply Current (average value of RAS-CAS cycles) Refresh Current (average value of RAS cycles) FPM Current (average value of FPM cycles) Stand-by Current (TTL Level)
2)
Max. Unit 08 07 70 08 60 mA
tcW = tcWmin tcR = tcRmin tcW = tcWmin tcR = tcRmin CAS = VIH tcPG = tcPGmin RAS = VIL RAS = CAS = VIH RAS = CAS = VCC - 0.2 V IOH = -5 mA IOL = 4.2 mA VI = 0 V to 5.5 V VO = 0 V to 5.5 V RAS = CAS = VIH
ICC1
2)
ICC2
70
60
mA
2)
ICC3
50
40
mA
ICC4
2
2
mA
Stand-by Current (CMOS Level)
ICC5
1
1
mA
Output High Voltage Output Low Voltage Input Leakage Current at any input, all other pins = 0 V Output Leakage Current Q = High-Z
VOH VOL II
2.4
2.4 0.4 0.4 10
V V A
-10
-10
10
IO
-10
-10
10
10
A
Remarks: see page 7
4
December 12, 1997
UD61256
Symbol Dynamic Characteristics
3)
Min. 07 08 07
Max. Unit 08
Alt.
IEC
F ALL CYCLES
Transition Time (Rise and Fall) RAS Precharge Time CAS Precharge Time Row Address Set-up Time Column Address Set-up Time Row Address Hold Time Column Address Hold Time Column Address Hold Time ref. to RAS Output Buffer Turn-off Delay CAS to RAS Precharge Time RAS to Column Address Delay Time Column Address to RAS Lead Time CAS to Output in Low-Z Refresh Period
5) 4)
tT tRP tCP tASR tASC
t RAH
tt
3 50 10 0 0 10 15 55 0 5 15 35 0
3 60 10 0 0 10 15 60 0 5 15 40 0
50
50
ns ns ns ns ns ns ns ns
tw(RASH) tw(CASH) tsu(RA-RAS) tsu(CA-CAS) th(RAS-RA) th(CAS-CA) th(RAS-CA) tv(CAS) tCASH-RASL tRAS-CA tCA-RASH tCASL-QX trf
tCAH tAR tOFF tCRP tRAD tRAL tCLZ tREF
20 35
20 40
ns ns ns ns ns ms
6)
4
4
F READ
Random Read Cycle Time Access Time from RAS Access Time from Column Address Access Time from CAS RAS Pulse Width CAS Pulse Width Read Command Set-up Time Read Command Hold Time ref. to RAS Read Command Hold Time RAS to CAS Delay Time CAS Hold Time RAS Hold Time
9) 9) 6) 12) 7), 8) 7), 8) 7), 8)
tRC tRAC tAA tCAC tRAS tCAS tRCS tRRH tRCH tRCD tCSH tRSH
tcR ta(RAS) ta(CA) ta(CAS) tw(RASL) tw(CASL) tsu(R-CAS) th(RAS-R) th(CAS-R) tRASL-CASL tRASL-CASH tCASL-RASH
130
150 70 35 20 80 40 20 10000 10000
ns ns ns ns ns ns ns ns ns 50 60 ns ns ns
70 20 0 0 0 20 70 20
80 20 0 0 0 20 80 20
10000 10000
F WRITE
Random Write Cycle Time RAS Pulse Width CAS Pulse Width Write Command Pulse Width Remarks: see page 7
12)
tRC tRAS tCAS tWP
tcW tw(RASL) tw(CASL) tw(W)
130 70 20 15
150 80 20 15 10000 10000 10000 10000
ns ns ns ns
December 12, 1997
5
UD61256
Symbol Dynamic Characteristics
3)
Min. 07 08 07
Max. Unit 08
Alt.
IEC
F WRITE (continuation)
Write Command Set-up Time Data Set-up Time ref. to CAS Data Set-up Time ref. to W Write Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time Data Hold Time ref. to RAS Data Hold Time ref. to CAS Data Hold Time ref. to W RAS to CAS Delay Time CAS Hold Time RAS Hold Time
6) 10) 11) 11)
tWCS tDS tDS tWCH tRWL tCWL tDHR tDH tDH tRCD tCSH tRSH
tsu(W-CAS) tsu(D-CAS) tsu(D-W) th(CAS-W) th(W-RAS) th(W-CAS) th(RAS-D) th(CAS-D) th(W-D) tRASL-CASL tRASL-CASH tCASL-RASH
0 0 0 15 20 20 55 15 15 20 70 20
0 0 0 15 20 20 60 15 15 20 80 20 50 60
ns ns ns ns ns ns ns ns ns ns ns ns
F READ-WRITE
Read-Write Cycle Time RAS Pulse Width CAS Pulse Width CAS Hold Time RAS to WRITE Delay Time CAS to WRITE Delay Time Column to WRITE Delay Time
12)
tRWC tRAS tCAS tCSH
tcRW tw(RASL)RW tw(CASL)RW t(RASLCASH)RW
155 95 45 95 70 20 35
175 105 45 105 80 20 40 10000 10000 10000 10000
ns ns ns ns ns ns ns
10) 10) 10)
F FPM
tRWD tCWD tAWD
tRAS-W tCAS-W t(CA-W)RW
Fast Page Mode Cycle Time RAS Pulse Width
12)
tPC tRASP tCPA
tcPG tw(RASL) ta(CASH)
50 70 35
50 80 40
100000 100000
ns ns ns
F HIDDEN-REFRESH
Remarks: see page 7
Access Time from CAS Precharge
CAS Hold Time (CAS before RAS Cycle)
tCHR
tRASL-CASH
15
15
ns
6
December 12, 1997
UD61256
Remarks:
1) 7)
The Input Low Voltage must not drop below -0.3 V for more than 40 ns. The current is inversely proportional to the cycle time; the max. current is measured in the shortest cycle time. For test conditions see test configuration for functional test and timing diagrams. VIHmin and VILmax are reference levels for time measurement of the input signals; transition times are measured between VIH and VIL. tv(CAS) and tv(RAS) define the time at which the data output goes to High-Z; this time is not related to any level. tRASL-CASLmax and tRAS-CA are given as reference points only; they do not represent restrictive conditions.
The access time is determined by the three times ta(RAS), ta(CAS) and ta(CA): - if tRASL-CASL < tRASL-CASLmax and tRAS-CA < tRAS-CAmax ta(RAS) is valid, - if tRASL-CASL > tRASL-CASLmax and tsu(CA-CAS) < (ta(CA)max - ta(CAS)max) t a(CA) is valid, - if tRASL-CASL > tRASL-CASLmax and tsu(CA-CAS) > (ta(CA)max - ta(CAS)max) t a(CAS) is valid.
- if tCAS-W > tCAS-Wmin, tRAS-W > tRAS-Wmin and tsu(CA-W)RW > tsu(CA-W)RWmin, the cycle is a READ-WRITE cycle and the content of the cell is available at the data output, - if none of these conditions is satisfied, the condition of the data output (at access time) is indeterminate, since a WRITE cycle (W-controlled) is carried out.
11)
2)
3)
4)
8)
Measured with a load equivalent to 2 TTL loads. In a READ cycle either th(RAS-R) or th(CAS-R) must be kept. tsu(W-CAS), tRAS-W, tCAS-W and tsu(A) do not represent restrictive parameters: - if tsu(W-CAS) tsu(W-CAS)min, the cycle is a WRITE cycle (CAScontrolled) and the data output remains in High-Z throughout the whole CAS cycle,
These parameters refer to CAS in the WRITE cycle (CAS-controlled) and to W during WRITE (W-controlled) or to W in the READ-WRITE cycle, resp. The values of tcmin are used for indication of the particular cycle time in which full function is guaranteed in the temperature range from 0 to 70 C. Values below the one shown above may cause permanent damage to the component.
9)
12)
5)
10)
6)
December 12, 1997
7
UD61256
Test Configuration for Functional Check
5V Input voltage according to timing diagrams (at least 8 operating cycles before measurement). All addresses are to be checked.
VIH
VIL
A0 A1 A2 A3 A4 A5 A6 A7 A8 RAS CAS W D
VCC 1,2 K
Q
100 pF 680
VSS
IC Code Numbers
UD61256 Type Package D = PDIP J = SOJ
D
C
07
Access Time 07 = 70 ns 08 = 80 ns Operating Temperature Range C = 0 to 70 C
The date of manufacture is given by the 4 last digits of the mark, the 2 first digits indicating the year, and the last 2 digits the calendar week.
8
Output voltage check according to timing diagrams
December 12, 1997
UD61256
Read
tcR tw(RASL) tw(RASH)
RAS
VIH VIL
tRA SL-CA SH tCA SH-RA SL tRA SL-CA SL
tCA SL-RASH tw(CASL)
tCA SH-RA SL
CAS
VIH VIL
tsu(R-CAS) tsu(CA -CAS) th(RA S-R) th(CA S-R)
W
VIH AAAAAAAAAAAAAA AAAAAAAAAAAAAA VIL AAAAAAAAAAAAAA
tsu(RA-RAS) th(RAS-CA ) th(RAS-RA ) th(CAS-CA )
tCA-RASH
AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA
V A0-A8 VIH AAAAA IL AAAAA AAAAAt VOH VOL
RAS-CA
AAA AAA AAA
ta(CA ) ta(RA S)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
ta(CA S) tv(CA S)
Q
AAAAAA AAAAAA AAAAAA
tCA SL-QX
Write (CAS-controlled)
tcW tw(RA SL) tw(RASH)
RAS
VIH VIL
tCA SH-RA SL tRASL-CASL
tRASL-CASH tCASL-RASH tw(CASL) tCA SH-RA SL
CAS
VIH VIL
tsu(W-CAS)
th(W-CAS) th(W-RA S) tw(W)
W
VIH AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAA th(RAS-CA)
tsu(RA -RA S) th(RAS-RA )
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
th(CAS-W) tCA-RASH
V AAAAA A0-A8 VIH AAAAA IL AAAAA
tsu(CA -CA S) tsu(D-CAS)
AAA AAA AAA
th(CA S-CA) th(RA S-D) th(CAS-D)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
D Q
VIH VIL VOH VOL
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
High-Z
December 12, 1997
9
UD61256
Read-Write
tcRW tw(RASL)RW tw(RA SH)
RAS
VIH VIL
tRASL-CASH tCA SH-RA SL tRASL-CASL tCASL-RASH tw(CA SL)RW tCASH-RASL
CAS
VIH VIL
tsu(R-CAS) tRAS-W tCAS-W
th(W-CAS) th(W-RA S)
W
VIH AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAA
tsu(RA -RAS) th(RAS-CA ) th(RAS-RA ) th(CAS-CA)
tw(W)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
V A0-A8 VIH AAAAA IL AAAAA AAAAA
AAAA AAAA AAAA tsu(CA-CAS)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
t(CA-W)RW tsu(D-W) th(W-D)
D
VIH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA t
a(CA S)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tv(CA S)
ta(CA ) ta(RAS)
Q
VOH VOL
tCA SL-QX
AAAAAAAA AAAAAAAA AAAAAAAA
FPM Read
tw(RA SL) tw(RA SH)
RAS
VIH VIL
tCASH-RASL tRA SL-CASH tRA SL-CA SL tw(CASL)
tcPG tw(CASH) tw(CA SL)
tcPG tw(CASH)
tCA SL-RA SH tw(CASL
CAS
VIH VIL
tsu(R-CA S) tsu(R-CA S) th(CAS-R) th(CAS-R) tsu(R-CA S) th(RA S-R) th(CAS-R)
W
VIH AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAA
tsu(RA-RAS)
tsu(CA-CAS) th(CAS-CA)
AAAAAAA AAAAAAA AAAAAAA
tsu(CA-CAS) th(CAS-CA )
AAAAAAA AAAAAAA AAAAAAA
tCA-RASH tsu(CA-CAS) th(CA S-CA)
AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
V AAAAA AAAAA A0-A8 VIH AAAAA IL th(RAS-RA )
tRAS-CA
ta(CAS) th(RAS-CA ) ta(CA)
AAAAAA AAAAAA AAAAAA
ta(CA) tCASL-QX
ta(CAS)
AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA
ta(CA ) tCASL-QX
ta(CAS)
AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA
Q
VOH VOL
tCA SL-QX ta(RA S)
AAAAA AAAAA AAAAA
tv(CAS) ta(CASH)
AAAA AAAA AAAA
tv(CAS) ta(CASH)
AAAAA AAAAA AAAAA
tv(CA S)
10
December 12, 1997
UD61256
FPM Write (CAS-controlled)
tw(RASL) tRA SL-CASH tw(RASH)
RAS
VIH VIL
tcPG tCASH-RASL tRA SL-CA SL tw(CASL) tw(CASH) tcPG tw(CA SL) tw(CA SH) tCA SL-RASH tw(CASL)
CAS
VIH VIL
tsu(W-CAS) tw(W) th(CA S-W) tw(W) th(CAS-W)
tw(W) th(CA S-W) th(W-RAS)
W
VIH VIL
AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
AAAAA AAAAA AAAAA
tsu(CA-CAS) th(CA S-CA) tsu(CA-CAS)
tsu(W-CA S) th(CAS-CA )
AAAAA AAAAA AAAAA
tsu(CA-CAS)
tsu(W-CA S) tCA -RA SH
AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
tsu(RA-RAS)
A0-A8 VIH AAAAAA VIL AAAAAA AAAAAA
th(RAS-RA )
th(RA S-CA)
AAAAAA AAAAAA AAAAAA
AAAAAAAAA AAAAAAAAA AAAAAAAAA
th(CA SL-D)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA t
h(CA S-CA)
th(CA SL-D)
th(CA SL-D)
D
VIH VIL
th(RA S-D) tsu(D-CAS)
AAAAAAAA AAAAAAAA AAAAAAAA
tsu(D-CA S)
AAAAAAAA AAAAAAAA AAAAAAAA
tsu(D-CAS)
AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA
Q
VOH VOL
High-Z
RAS only Refresh
tcR tw(RA SL) tw(RASH)
RAS
VIH VIL
tCA SH-RA SL
CAS
VIH VIL
W
VIH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA
tsu(RA-RAS) th(RA S-RA)
V A0-A8 VIH AAAAAA AAAAAA IL AAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
D
VIH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Q
VOH VOL 11
High-Z
December 12, 1997
UD61256
HIDDEN-Refresh with address transfer
tcR tw(RA SL) tw(RASH)
tcR tw(RA SL)
tw(RASH)
RAS
VIH VIL
tCASH-RASL tRASL-CASL tCASL-RASH tRA SL-CA SH tCASH-RASL
CAS
VIH VIL
tsu(R-CAS) th(RA S-R)
W
VIH AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAA
th(RA S-CA) tsu(RA-RAS) th(RA S-RA) tCA -RA SH ta(CA) ta(CA S) tCASL-QX
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
th(RAS-RA ) tsu(RA -RA S)
AAAAAAAA A0-A8 VIH AAAAAAAA AAAAAAAA VIL
tRAS-CA
AAAAA AAAAA AAAAA
AAAAAAAAA AAAAAAAAA AAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tv(CAS)
Q
VOH VOL
ta(RAS)
AAAAAA AAAAAA AAAAAA
12
December 12, 1997
Memory Products 1998 256K x 1 DRAM UD61256
LIFE SUPPORT POLICY ZMD products are not designed, intended, or authorized for use as components in systems intend for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ZMD product could create a situation where personal injury or death may occur. Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved.
Zentrum Mikroelektronik Dresden GmbH Grenzstrae 28 * D-01109 Dresden * P. O. B. 80 01 34 * D-01101 Dresden * Germany Phone: +49 351 88 22-3 06 * Fax: +49 351 88 22-3 37 * Email: sales@zmd.de Internet Web Site: http://www.zmd.de

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